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IS43R16320A
32Meg x 16 512-MBIT DDR SDRAM
FEATURES DEVICE OVERVIEW
ISSI
MARCH 2006
(R)
* * * * * * * * * * * * * * * * * *
Clock Frequency: 166 MHz Power supply (VDD and VDDQ) DDR 333: 2.5V + 0.2V SSTL 2 interface Four internal banks to hide row Pre-charge and Active operations Commands and addresses register on positive clock edges (CK) Bi-directional Data Strobe signal for data capture Differential clock inputs (CK and CK) for two data accesses per clock cycle Data Mask feature for Writes supported DLL aligns data I/O and Data Strobe transitions with clock inputs Programmable burst length for Read and Write operations Programmable CAS Latency (2 or 2.5 clocks) Programmable burst sequence: sequential or interleaved Burst concatenation and truncation supported for maximum data throughput Auto Pre-charge option for each Read or Write burst 8192 refresh cycles every 64ms Auto Refresh and Self Refresh Modes Pre-charge Power Down and Active Power Down Modes Lead-free package
ISSI's 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 16-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CK. Commands are registered on the positive edges of CK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable (CKE) and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL 2.
KEY TIMING PARAMETERS
Parameter Clock Cycle Time CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 -6 DDR333 -- 6 7.5 -- 166 133 ns ns ns MHz MHz MHz Unit
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/06
1
IS43R16320A
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD DNU LDM WE CAS RAS CS NC BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
ISSI
(R)
PIN DESCRIPTIONS
A0-A12 A0-A9 BA0, BA1 DQ0 to DQ15 CK, CK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDM, UDM LDQS, UDQS VDD Vss VDDQ VssQ VREF DNU NC 2 Write Enable x16 Input Mask Data Strobe Power Ground Power Supply for I/O Pin Ground for I/O Pin Input Reference Voltage Do Not Use No Connection
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/06
IS43R16320A
Mode Register Operation
BA1 0* BA0 0* A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0
ISSI
Address Bus Mode Register Operating Mode CAS Latency Burst Length
(R)
A12 - A9 0 0
A8 0 1
A7 0 0
A6 - A0 Valid Valid
Operating Mode Normal operation Do not reset DLL Normal operation in DLL Reset Reserved A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length
A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
* BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).
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IS43R16320A
Burst Definition
Burst Length Starting Column Address A2 A1 A0 0 2 0 0 4 1 1 0 0 0 0 8 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
ISSI
Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
(R)
Notes: 1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition. Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR333. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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IS43R16320A
Read Command
ISSI
CK CK CKE CS RAS CAS WE CA EN AP A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care HIGH
(R)
A0-A9
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IS43R16320A
Write Command
ISSI
CK CK CKE CS RAS CAS WE A0-A9 CA EN AP A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care HIGH
(R)
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IS43R16320A
Capacitance
Parameter Input Capacitance: CK, CK Delta Input Capacitance: CK, CK Input Capacitance: All other input-only pins (except DM) Delta Input Capacitance: All other input-only pins (except DM) Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS, DM Symbol CI1 delta CI1 CI2 delta CI2 CIO delta CIO 4.0 2.0 Min. 2.0 Max. 3.0 0.25 3.0 0.5 5.0 0.5 Units pF pF pF pF pF pF
ISSI
Notes 1 1 1 1 1, 2 1
(R)
1. VDDQ = VDD = 2.5V 0.2V (minimum range to maximum range), f = 100MHz, TA = 25C, VODC = VDDQ/2, VOPeak -Peak = 0.2V. 2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
(0C < T A < 70oC; VDDQ = VDD = + 2.5V 0.2V (DDR333); see AC Characteristics)
Symbol VDD VDDQ Supply Voltage DDR 333 I/O Supply Voltage DDR333
Parameter
Min 2.3 2.3
Max 2.7 2.7
Units V V
Notes 1 1
VSS, VSSQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) VIRatio II IOZ
Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs V-I Matching Pullup Current to Pulldown Current Ratio Input Leakage Curr ent Any input 0V < VIN < VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V < Vout < VDDQ
0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.30 0.30 0.71
-2 -5
0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 1.4
2 5
V
V 1, 2
V V V V V V
1, 3 1 1 1 1, 4 1, 4 5
A A
1 1
1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
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IS43R16320A
DC Electrical Characteristics and Operating Conditions
(0C < T A < 70oC; VDDQ = VDD = + 2.5V 0.2V (DDR333); see AC Characteristics)
ISSI
Parameter Min - 16.8 16.8 - 9.0 9.0 Max Units mA Notes 1
(R)
Symbol IOH IOL IOHW IOLW
Output Current: Nominal Strength Driver High current (VOUT= VDDQ -0.373V, min VREF, min VTT) Low current (VOUT= 0.373V, max VREF, max VTT) Output Current: Half- Strength Driver High current (VOUT= VDDQ -0.763V, min VREF, min VTT) Low current (VOUT= 0.763V, max VREF, max VTT)
mA
1
1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
Normal Strength Driver Pulldown and Pullup Characteristics
1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 2. It is recommended that the "typical" IBIS pulldown V-I curve lie within the shaded region of the V-I curve.
Normal Strength Driver Pulldown Characteristics
140 Maximum Typical High Typical Low Minimum
IOUT (mA) 0 0
VOUT (V)
2.7
3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 4. It is recommended that the "typical" IBIS pullup V-I curve lie within the shaded region of the V-I curve.
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IS43R16320A
Normal Strength Driver Pullup Characteristics
0 Minimum IOUT (mA) Typical Low
ISSI
(R)
Typical High -200 0 VOUT (V) 2.7 Maximum
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity + 10%, for device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed. 7. These characteristics are intended to obey the SSTL_2 class II standard. 8. This specification is intended for DDR SDRAM only.
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IS43R16320A
Normal Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Typical Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Typical High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Min 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Max 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Typical Low -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Typical High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Min -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2
ISSI
Max -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
(R)
Normal Strength Driver Evaluation Conditions
Typical Temperature (Tambient) VDDQ Process conditions 25 C 2.5V typical process Minimum 70 C 2.3V slow-slow process Maximum 0 C 2.7V fast-fast process
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IS43R16320A
AC Characteristics
ISSI
(R)
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level.
AC Output Load Circuit Diagrams
VTT
50 Output (VOUT)
Timing Reference Point
30pF
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IS43R16320A
AC Input Operating Conditions
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 1. 2. 3. 4.
(0 C < TA < 70o C VDD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics)
ISSI
Parameter/Condition Min VREF + 0.31 VREF - 0.31 0.62 0.5*VDDQ - 0.2 VDDQ + 0.6 0.5*VDDQ + 0.2 Max Unit V V V V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4
(R)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs
Input slew rate = 1V/ns Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
IDD Specifications and Conditions
Symbol
(0 C < TA < 70oC V DD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics)
Parameter/Condition Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power Down Standby Current: all banks idle; Power Down mode; CKE < VIL (max) Idle Standby Current: CS > VIH (min); all banks idle; CKE > VIH (min); address and control inputs changing once per clock cycle Active Power Down Standby Current: one bank active; Power Down mode; CKE < VIL (max) Active Standby Current: one bank; active / precharge; CS > VIH (min); CKE > VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5 Auto-Refresh Current: tRC = tRFC (min) Self-Refresh Current: CKE < 0.2V Operating current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA.
DDR333 (6K) tCK=6ns 96
Unit
Notes
IDD0
mA
1
IDD1 IDD2P IDD2N IDD3P
99
mA
1
5 25
mA mA
1 1
11
mA
1
IDD3N
45
mA
1
IDD4R
104
mA
1
IDD4W IDD5 IDD6 IDD7
117 193 5
mA mA mA
1 1 1, 2
307
mA
1
1. IDD specifications are tested after the device is properly initialized. 2. Enables on-chip refresh and address counters. Values are averaged from high and low temp values using x16 devices.
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IS43R16320A
Electrical Characteristics & AC Timing - Absolute Specifications
(0 C < TA < 70 oC VDD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics) Symbol Parameter DDR333 (6K) Min tAC DQ output access time from CK/CK -0.7 -0.6 0.45 0.45 CL = 3.0 tCK Clock cycle time CL = 2.5 CL = 2.0 tDH tDS tIPW tDIPW tHZ tLZ DQ and DM input hold time DQ and DM input setup time Input pulse width DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK TSOP Package BGA Package min (tCL, tCH) tHP - tQHS TSOP Package BGA Package Write command to 1st DQS latching transition 0.75 0.35 0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.75 0.8 0.8 0.9 0.40 1.1 0.60 0.60 0.55 0.5 1.25 6 7.5 0.45 0.45 2.2 1.75 -0.7 -0.7 +0.7 +0.7 +0.45 +0.4 12 12 Max +0.7 +0.6 0.55 0.55 ns ns tCK tCK ns ns ns ns ns ns ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns tCK tCK ns ns ns ns tCK tCK 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 15, 16 1-4, 15, 16 2-4, 12 1-4 1-4, 5 1-4, 5 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, 10-12, 14 2-4, 10, 11, 12, 14 1-4 1-4 Unit Notes
ISSI
(R)
tDQSCK DQS output access time from CK/CK tCH tCL CK high-level width CK low-level width
tDQSQ DQS-DQ skew (DQS & associated DQ signals) tHP tQH tQHS tDQSS Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time Data output hold time from DQS Data hold Skew Factor
tDQSH DQS input high pulse width (write cycle) tDQSL tDSS tDSH tMRD DQS input low pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time
tWPRES Write preamble setup time tWPST Write postamble
tWPRE Write preamble tIH tIS tIH tIS tRPRE tRPST Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Read preamble Read postamble
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IS43R16320A
Electrical Characteristics & AC Timing - Absolute Specifications
(0 C < TA < 70 oC VDD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics) Symbol Parameter DDR333 (6K) Min tRAS tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tPDEX tXSNR tXSRD tREFI Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Autoprecharge Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Power down exit time Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval 42 60 72 18 min (tRCD, tRAS) 18 12 15 (tWR/tCK) + (tRP/tCK) 1 6 75 200 7.8 Max 120,000 ns ns ns ns ns ns ns ns tCK tCK ns ns tCK us 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 13 1-4 1-4 1-4 1-4 1-4, 8 Unit Notes
ISSI
(R)
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IS43R16320A
Electrical Characteristics & AC Timing - Absolute Specifications Notes
ISSI
(R)
1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are 1.0V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for DDR333 at CL = 2.5, t DAL = (15ns/6ns) + (18ns/6ns) = 3 + 3 = 6.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/06
15
IS43R16320A
rate is below 0.5 V/ns.
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta (tIS) 0 +50 +100 delta (tIH) 0 0 0 Unit ps ps ps
ISSI
Notes 1,2 1,2 1,2
(R)
14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta (tDS) 0 +75 +150 delta (tDH) 0 +75 +150 Unit ps ps ps Notes 1,2 1,2 1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ.
Input Slew Rate 0.0 V/ns 0.25 V/ns 0.5 V/ns delta (tDS) 0 +50 +100 delta (tDH) 0 +50 +100 Unit ps ps ps Notes 1,2,3,4 1,2,3,4 1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/06
IS43R16320A
ISSI
Order Part No. IS43R16320A-6TL Package 66-pin TSOP-II, Lead-free
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C
Frequency 166 MHz Speed (ns) 6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/22/06
17
PACKAGING INFORMATION
Plastic TSOP 66-pin Package Code: T (Type II)
ISSI
N/2+1 E1 E
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
(R)
N
measured from the bottom of the package.
1 D
N/2
ZD
A
SEATING PLANE
e
b
A1
L
C
Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 66 A A1 A2 b C D E1 E e L L1 ZD -- 1.20 0.05 0.15 -- -- 0.24 0.40 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.65 BSC 0.40 0.60 -- -- 0.71 REF 0 8 -- 0.047 0.002 0.006 -- -- 0.009 0.016 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.026 BSC 0.016 0.024 -- -- 0.028 REF 0 8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 08/09/05
1

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